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Honored Contributor
Honored Contributorabout state machine
i want to write a state machine.but quartus ii report error. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity p159 is port( clk,clr,input:in std_logi...
Altera_ForumHonored Contributor
Honored Contributorits a syntax error on line 15 (actually, theres more than that).
the error is here: if clr='0' then s=s0; it needs to be s <= s0; in VHDL <= is used for assignment of signals, := for variables. = is just an equality operator.
