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Honored Contributor
Honored Contributorabout ram_2_port ip core
In my project I used the ip core (ram_2_port).I add avalon_tristate_slave for the ram2port in the sopc builer.But I can't write to the ram2port_base.When I write 0x00 to the ram2port_base,it write to...
Altera_ForumHonored Contributor
Honored Contributorare the data widths of the master and slave the same? is the component a register slave or a memory slave, ie is it using dynamic bus sizing?
--dalon
