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Altera_Forum
Honored Contributor
Honored ContributorAbout path delay in my FPGA
My dear, My application is that a signal EN_in to my FPGA , and a EN_out from my FPGA to ADCs. Now I want to delay the signal for unknown ns to need the ADC timing,the detail ns is test by my team...
Altera_ForumHonored Contributor
Honored ContributorYou can't use timing constraints (set_min/max_delay) to add delay to your output signals. That's not what they're used for.
If you really want to stagger 8 signals with a 1ns delay between them you'd need a 1GHz clock. Cheers, Alex
