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lambert_yu's avatar
lambert_yu
Icon for Contributor rankContributor
5 years ago

About pad scheme of i3c prototype on fpga

Hi all,

I want to build one i3c prototype on fpga, but I find that all pins can only used as one of the push-pull or open-drain, I don't find that one pin can switch drive mode between push-pull and open-drain, anyone can provide me some advice, thanks.

Best regards,

Lambert

5 Replies

  • NurAiman_M_Intel's avatar
    NurAiman_M_Intel
    Icon for Super Contributor rankSuper Contributor
    5 years ago

    Hi,


    Thank you for contacting Intel community.


    May i know what is the device number for the FPGA?


    Thanks.


    Regards,

    Aiman


    • lambert_yu's avatar
      lambert_yu
      Icon for Contributor rankContributor
      5 years ago

      Hi airman,

      I have cyclone v, arria v, arria 10, cyclone 10 board, but I don’t find which one can fulfill my need, or can you provide some advice or fpga kind which can resolve my problem, thanks.

      Best Regards,

      Lambert

  • ak6dn's avatar
    ak6dn
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    You'll find in FPGAs the operating characteristics of a pin are not dynamically settable (ie, LVCMOS vs LVTTL vs LVDS, etc), dynamic pullups, bus hold, totem-pole vs open collector. They can be programmed at startup but are hard (but not necessarily impossible) to change dynamically.

    A driver enable can enable/disable the driver function, but it is an all or none option.

    Simplest is probably to assign two adjacent pins, an open collector driver with enable, and a totem-pole driver with enable. Then chose one to sample input on, and enable one driver or the other as needed.

    • Lambert's avatar
      Lambert
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago
      Hi ak6dn
      So maybe I can use this method currently, and will such pins appear in new FPGA models in the future?

      B.R,
      Lambert
      • ak6dn's avatar
        ak6dn
        Icon for Regular Contributor rankRegular Contributor
        5 years ago

        So maybe I can use this method currently, and will such pins appear in new FPGA models in the future?

        Since I don't work for Intel/Altera, I can't make any comment on this other than 'not likely', in my opinion.

        The usage scenario is quite small for this feature, and using two pins vs one is not a big deal in that case.

        It is not like you are going to build a controller that needs hundreds of 'I3C' interfaces.