About pad scheme of i3c prototype on fpga

You'll find in FPGAs the operating characteristics of a pin are not dynamically settable (ie, LVCMOS vs LVTTL vs LVDS, etc), dynamic pullups, bus hold, totem-pole vs open collector. They can be programmed at startup but are hard (but not necessarily impossible) to change dynamically.

A driver enable can enable/disable the driver function, but it is an all or none option.

Simplest is probably to assign two adjacent pins, an open collector driver with enable, and a totem-pole driver with enable. Then chose one to sample input on, and enable one driver or the other as needed.