Contributor
Regular ContributorYou'll find in FPGAs the operating characteristics of a pin are not dynamically settable (ie, LVCMOS vs LVTTL vs LVDS, etc), dynamic pullups, bus hold, totem-pole vs open collector. They can be programmed at startup but are hard (but not necessarily impossible) to change dynamically.
A driver enable can enable/disable the driver function, but it is an all or none option.
Simplest is probably to assign two adjacent pins, an open collector driver with enable, and a totem-pole driver with enable. Then chose one to sample input on, and enable one driver or the other as needed.
Occasional ContributorRegular ContributorSo maybe I can use this method currently, and will such pins appear in new FPGA models in the future?
Since I don't work for Intel/Altera, I can't make any comment on this other than 'not likely', in my opinion.
The usage scenario is quite small for this feature, and using two pins vs one is not a big deal in that case.
It is not like you are going to build a controller that needs hundreds of 'I3C' interfaces.
