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https://alteraforum.com/forum/attachment.php?attachmentid=15791&stc=1 Dear Friends！
when I working on CvP confgures the FPGA fabric through the PCI Express® (PCIe) link ，I get the errors：
ERROR：Timed out while waiting for CVP_CONFIG_READY == 0
ERROR : Timed out while polling the PLD_CLK_IN_USE and USER_MODE bits
the errors as you see on the picture.the vesion of the software which I use is 16.1 . the OS is windows 7. I cannot get more information about the errors on the line .
Look forward to your reply！！
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is there anyone to konw it?
Honored Contributor
