About ALTIOBUF simulation

thanks Aqid, in fact I'm trying to simulate the IOBUF, which is generated by IP catalog, and compilation cannot pass, attached is the generated file, FYI.

-- megafunction wizard: %ALTIOBUF%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altiobuf_in

-- ============================================================

-- File Name: IN_delay_buf.vhd

-- Megafunction Name(s):

-- altiobuf_in

--

-- Simulation Library Files(s):

-- cyclonev

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 17.1.0 Build 590 10/25/2017 SJ Standard Edition

-- ************************************************************

--Copyright (C) 2017 Intel Corporation. All rights reserved.

--Your use of Intel Corporation's design tools, logic functions

--and other software and tools, and its AMPP partner logic

--functions, and any output files from any of the foregoing

--(including device programming or simulation files), and any

--associated documentation or information are expressly subject

--to the terms and conditions of the Intel Program License

--Subscription Agreement, the Intel Quartus Prime License Agreement,

--the Intel FPGA IP License Agreement, or other applicable license

--agreement, including, without limitation, that your use is for

--the sole purpose of programming logic devices manufactured by

--Intel and sold by Intel or its authorized distributors. Please

--refer to the applicable agreement for further details.

--altiobuf_in CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 USE_DIFFERENTIAL_MODE="FALSE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" USE_IN_DYNAMIC_DELAY_CHAIN="TRUE" datain dataout io_config_clk io_config_clkena io_config_datain io_config_update

--VERSION_BEGIN 17.1 cbx_altiobuf_in 2017:10:25:18:06:52:SJ cbx_mgl 2017:10:25:18:08:29:SJ cbx_stratixiii 2017:10:25:18:06:53:SJ cbx_stratixv 2017:10:25:18:06:53:SJ VERSION_END

LIBRARY cyclonev;

USE cyclonev.all;

--synthesis_resources = cyclonev_delay_chain 1 cyclonev_io_config 1 cyclonev_io_ibuf 1

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY IN_delay_buf_iobuf_in_3jr IS

PORT

(

datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);

io_config_clk : IN STD_LOGIC := '0';

io_config_clkena : IN STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');

io_config_datain : IN STD_LOGIC := '0';

io_config_update : IN STD_LOGIC := '0'

);

END IN_delay_buf_iobuf_in_3jr;

ARCHITECTURE RTL OF IN_delay_buf_iobuf_in_3jr IS

SIGNAL wire_sd1_dataout : STD_LOGIC;

SIGNAL wire_sd1_delayctrlin : STD_LOGIC_VECTOR (4 DOWNTO 0);

SIGNAL wire_ioconfiga_padtoinputregisterdelaysetting : STD_LOGIC_VECTOR (4 DOWNTO 0);

SIGNAL wire_ibufa_o : STD_LOGIC_VECTOR (0 DOWNTO 0);

COMPONENT cyclonev_delay_chain

GENERIC

(

sim_falling_delay_increment : NATURAL := 10;

sim_intrinsic_falling_delay : NATURAL := 200;

sim_intrinsic_rising_delay : NATURAL := 200;

sim_rising_delay_increment : NATURAL := 10;

lpm_type : STRING := "cyclonev_delay_chain"

);

PORT

(

datain : IN STD_LOGIC := '0';

dataout : OUT STD_LOGIC;

delayctrlin : IN STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0')

);

END COMPONENT;

COMPONENT cyclonev_io_config

GENERIC

(

enhanced_mode : STRING := "false";

lpm_type : STRING := "cyclonev_io_config"

);

PORT

(

clk : IN STD_LOGIC := '0';

datain : IN STD_LOGIC := '0';

dataout : OUT STD_LOGIC;

dutycycledelaysettings : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

ena : IN STD_LOGIC := '0';

outputenabledelaysetting : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);

outputfinedelaysetting1 : OUT STD_LOGIC;

outputfinedelaysetting2 : OUT STD_LOGIC;

outputhalfratebypass : OUT STD_LOGIC;

outputonlydelaysetting2 : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);

outputonlyfinedelaysetting2 : OUT STD_LOGIC;

outputregdelaysetting : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);

padtoinputregisterdelaysetting : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);

padtoinputregisterfinedelaysetting : OUT STD_LOGIC;

readfifomode : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);

readfiforeadclockselect : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);

update : IN STD_LOGIC := '0'

);

END COMPONENT;

COMPONENT cyclonev_io_ibuf

GENERIC

(

bus_hold : STRING := "false";

differential_mode : STRING := "false";

simulate_z_as : STRING := "z";

lpm_type : STRING := "cyclonev_io_ibuf"

);

PORT

(

dynamicterminationcontrol : IN STD_LOGIC := '0';

i : IN STD_LOGIC := '0';

ibar : IN STD_LOGIC := '0';

o : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

dataout(0) <= ( wire_sd1_dataout);

wire_sd1_delayctrlin <= ( wire_ioconfiga_padtoinputregisterdelaysetting(4 DOWNTO 0));

sd1 : cyclonev_delay_chain

PORT MAP (

datain => wire_ibufa_o(0),

dataout => wire_sd1_dataout,

delayctrlin => wire_sd1_delayctrlin

);

ioconfiga : cyclonev_io_config

PORT MAP (

clk => io_config_clk,

datain => io_config_datain,

ena => io_config_clkena(0),

padtoinputregisterdelaysetting => wire_ioconfiga_padtoinputregisterdelaysetting,

update => io_config_update

);

ibufa : cyclonev_io_ibuf

GENERIC MAP (

bus_hold => "false",

differential_mode => "false"

)

PORT MAP (

i => datain(0),

o => wire_ibufa_o(0)

);

END RTL; --IN_delay_buf_iobuf_in_3jr

--VALID FILE

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY IN_delay_buf IS

PORT

(

datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

io_config_clk : IN STD_LOGIC ;

io_config_clkena : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

io_config_datain : IN STD_LOGIC ;

io_config_update : IN STD_LOGIC ;

dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

);

END IN_delay_buf;

ARCHITECTURE RTL OF in_delay_buf IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);

COMPONENT IN_delay_buf_iobuf_in_3jr

PORT (

datain : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

io_config_clk : IN STD_LOGIC ;

io_config_clkena : IN STD_LOGIC_VECTOR (0 DOWNTO 0);

io_config_datain : IN STD_LOGIC ;

io_config_update : IN STD_LOGIC ;

dataout : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)

);

END COMPONENT;

BEGIN

dataout <= sub_wire0(0 DOWNTO 0);

IN_delay_buf_iobuf_in_3jr_component : IN_delay_buf_iobuf_in_3jr

PORT MAP (

datain => datain,

io_config_clk => io_config_clk,

io_config_clkena => io_config_clkena,

io_config_datain => io_config_datain,

io_config_update => io_config_update,

dataout => sub_wire0

);

END RTL;

-- ============================================================

-- CNX file retrieval info

-- ============================================================

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"

-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"

-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"

-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"

-- Retrieval info: CONSTANT: use_differential_mode STRING "FALSE"

-- Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"

-- Retrieval info: CONSTANT: use_in_dynamic_delay_chain STRING "TRUE"

-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"

-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"

-- Retrieval info: USED_PORT: io_config_clk 0 0 0 0 INPUT NODEFVAL "io_config_clk"

-- Retrieval info: USED_PORT: io_config_clkena 0 0 1 0 INPUT NODEFVAL "io_config_clkena[0..0]"

-- Retrieval info: USED_PORT: io_config_datain 0 0 0 0 INPUT NODEFVAL "io_config_datain"

-- Retrieval info: USED_PORT: io_config_update 0 0 0 0 INPUT NODEFVAL "io_config_update"

-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0

-- Retrieval info: CONNECT: @io_config_clk 0 0 0 0 io_config_clk 0 0 0 0

-- Retrieval info: CONNECT: @io_config_clkena 0 0 1 0 io_config_clkena 0 0 1 0

-- Retrieval info: CONNECT: @io_config_datain 0 0 0 0 io_config_datain 0 0 0 0

-- Retrieval info: CONNECT: @io_config_update 0 0 0 0 io_config_update 0 0 0 0

-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0

-- Retrieval info: GEN_FILE: TYPE_NORMAL IN_delay_buf.vhd TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL IN_delay_buf.inc FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL IN_delay_buf.cmp TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL IN_delay_buf.bsf FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL IN_delay_buf_inst.vhd FALSE

-- Retrieval info: LIB_FILE: cyclonev