A very simple problem about FPGA I/O Status

You can not disable this reduction, you can tell it to optimize the design for speed or area.

However in this case, the reduction would still be the same. Since you "Don't Care" what the initial condition is, and you can ONLY have a set condition of 1, it will reduce the logic to a 1 all the time.

The first stage of synthesis is to map all the logic then reduce it as much as possible using boolean logic reduction rules. Once that is done, it will then look at timing and area constraints and remap the logic a second time.

Pete