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Honored Contributor
Honored ContributorA very basic newbie question
Hi All I have a very basic question. I've recently started learning about CPLD and VHDL. My VHDL code usually compiles and simulates fine, but when I put it in an actual CPLD it behaves really...
Altera_ForumHonored Contributor
Honored ContributorGood to hear you solved your problem Haplo.
Your chip obviously has more pins than you are actually using in your FPGA design. Previously the pins that you weren't using in the FPGA were driving low because of that setting. Either one of those pins is driving some output on some other chip or has a short to something nasty and causing weird behaviour. Personally I usually make sure that I set unused pins to tri-state. If you had a load of tracks that are connected to unused stuff which might cause signal integrity problems if left floating, then you could fix these to a safe level in your design. If all is working then you probably don't need to worry about this - leave unused pins as tri-state. Well done. Batfink
