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Honored Contributor
Honored ContributorA very basic newbie question
Hi All I have a very basic question. I've recently started learning about CPLD and VHDL. My VHDL code usually compiles and simulates fine, but when I put it in an actual CPLD it behaves really...
Altera_ForumHonored Contributor
Honored ContributorI agree with FvM and OrchestraDirector - using variables rather than signals should make no difference (check your roll-over though - I have a feeling that you may not actually display the digit 9).
What is your master clock speed? Try slowing that down. Although in principle there is nothing necessarily wrong with using two clocks as you have done, clocks/global signals are generally not in abundance in FPGAs/PLDs. Personally I would generate a clock enable pulse rather than another clock and then use a clock enabled register to drive the display. Have you set a clock frequnecy in Quartus? Are there any timing violaations? Have you tried a gate level simulation? I can't see any glaring errors in your code - it looks basically OK. Cheers batfink
