A question regarding MAX II I/O supply voltage

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I am expecting to see roughly a Vih and Vil of 0.65*Vccio and 0.35*Vccio respectively, and a Voh and Vol of 0.75*Vccio and 0.25*Vccio respectively.

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That's reasonable. MAX II I/Os are CMOS gates supplied by VCCIO, they have a slight threshold asymmetry to better fit the LVTTL requirements, but basically comply with respective JEDEC level specification over the 1.5 to 3.3V supply range.

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whether it is a problem to connect the VCCIO pins of the MAX II device to a non-standard voltage, lets say for example 2.75v

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Obviously the MAX II specification is based on discrete I/O voltages, but you can't find a reason in the datasheet, why any value between 1.5 and 3.3 V shouldn't work as well.

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but you must take care about the voltage levels VioH and VioL so choose the correct io behavioral (VTLL VCMOS ....)

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Although you can specify I/O-standards for MAX II pins in the Quartus software, nothing is actually changed in configuration bitstream. Only current strength and activation of S/T input are real hardware features, the rest is for calculation of nominal current strength and checking of suitable bank voltage assignments.

Thanks for the swift reply.

My question was directed towards a voltage which is not specified in the data sheet, so obviously the Vih and Vil would not hold for an upper or lower voltage. For example if I'm connecting the Vccio to 2.75v, I don't expect the Vih and Vil levels to be either that of 3.3v or 2.5v.

I am expecting to see roughly a Vih and Vil of 0.65*Vccio and 0.35*Vccio respectively, and a Voh and Vol of 0.75*Vccio and 0.25*Vccio respectively.

as fas as i had understood the vccio pins too, and used them, you apply the voltage on these pins for particular io bank's

for example on a cyclone III designe here, the external sdram runs at 3,0V so the vccio pins for these io's is also connected to 3,0v to enshure this interface runs at that voltage. 3,0 V due to the 3,3V IO theme with cyclone III.

so yes it is correct what you say, but you must take care about the voltage levels VioH and VioL so choose the correct io behavioral (VTLL VCMOS ....)