Forum Discussion
Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- I am expecting to see roughly a Vih and Vil of 0.65*Vccio and 0.35*Vccio respectively, and a Voh and Vol of 0.75*Vccio and 0.25*Vccio respectively. --- Quote End --- That's reasonable. MAX II I/Os are CMOS gates supplied by VCCIO, they have a slight threshold asymmetry to better fit the LVTTL requirements, but basically comply with respective JEDEC level specification over the 1.5 to 3.3V supply range.