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Honored Contributora question about rapidio 1x
Dear: Now I want to use rapidio 1x to communicate with TMS320C6455, The FPGA is stratix V. I don't want to use Qsys, so i use Avalon-ST Pass-Through Interface to instead it. is it right?...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- By default, Avalon-ST transfers the first symbol (byte) in the MSB of the data. Looking at the header for gen_tx_data from the table, with an 32-bit interface, "ackID" is going to be on bits [31:27] of the first word of the transfer, while "sourceID" is going to be on bits [31:16] of the second word of the transfer. In other words, the fields come in the same order (working from MSB->LSB ), you just need 2x as many cycles to transfer the data. --- Quote End --- The Figure 4–32 is a NREAD example. If i want to use SWRITE, what is the the format of gen_tx_data Bus. I know the Ftype and Ttype should be changed, but i can't find the Destination Address(not deviceID). In RapidIO II MegaCore Function, Table 4–25 give the formate of gen_tx_data very clear, but i can't find the formate of gen_tx_data in RapidIO MegaCore Function. Looking forward to your reply! Thank you!
