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Altera_Forum's avatar
Altera_Forum
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11 years ago

a question about rapidio 1x

Dear: Now I want to use rapidio 1x to communicate with TMS320C6455, The FPGA is stratix V. I don't want to use Qsys, so i use Avalon-ST Pass-Through Interface to instead it. is it right?...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

By default, Avalon-ST transfers the first symbol (byte) in the MSB of the data. Looking at the header for gen_tx_data from the table, with an 32-bit interface, "ackID" is going to be on bits [31:27] of the first word of the transfer, while "sourceID" is going to be on bits [31:16] of the second word of the transfer.

In other words, the fields come in the same order (working from MSB->LSB ), you just need 2x as many cycles to transfer the data.