A problem with Cyclone/Arria 10GX Transciever

HI,

The best way to help you is to introduce TSE 1G example design to you as reference to cross check with your own design.

• https://fpgacloud.intel.com/devstore/platform/15.0.0/Standard/arria-10-single-port-triple-speed-ethernet-and-on-board-phy-chip-design/

Thanks.

Regards,

dlim

Thank you for your answer but this project is based on Marvell 88E1111 chip and I need a direct connection between FPGA and SFP. Moreover, the project uses LVDS I/O instead of GX functions. My PCB uses GX functions and pins. Should I use TSE or Native PHY and can you give me any applicable example?

HI,

I see. Unfortunately our TSE IP reference design is based on what I shared with you using LVDS IO.

On the other hand, NativePHY IP itself is just a skeleton IP where we freely allow customer to build any custom protocol solution on top of it. There won't be any reference design on it as reference design is developed to target certain application protocol.

For your case, the more appropriate reference design for you will be Ethernet PHY IP that can run on 1G.

You can checkout below LL Ethernet 10G MAC IP where you can customize the setting to generate Ethernet MAC + PHY example design that support 1G application.

• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_32b_10g_ethernet_mac.pdf

Thanks.

Regards,

dlim

Below is the link to list of Ethernet IP solution offered by Intel FPGA but I can't promise you we have reference design ready for all these IP.

• https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/ethernet-support.html

Thanks.

Regards,

dlim

HI,

I don't hear back from you after my feedback.

Hopefully you are doing well with your project development

For now, I am setting this case to closure.

Thanks.

Regards,

dlim