A PLL problem.

I see. To what item in the timing analyzer report should I pay attention. Going through the report couldn't find a clue.

I have a project with the same ADC module that compiles nad runs good. I compare two reports

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Source assignments for adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll
Source assignments for adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_stdsync_sv6:stdsync2|adc_qsys_ADC1_PLL_dffpipe_l2c:dffpipe3

Port Connectivity Checks: "adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_altpll_gr22:sd1"
Port Connectivity Checks: "adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll"

------------------ BAD PROJECT -----------------------

Source assignments for adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll
Source assignments for adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_stdsync_sv6:stdsync2|adc_qsys_ADC1_PLL_dffpipe_l2c:dffpipe3

Port Connectivity Checks: "adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_altpll_gr22:sd1"
Port Connectivity Checks: "adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll"

The two reports are the same. But the Fitter reports are different. And Fitter processed on earlier stage, before timing analyzer.

------------------ GOOD PROJECT -----------------------

+------------------------------------------------------------------------------------------------------+
; PLL Summary ;
+-------------------------------+----------------------------------------------------------------------+
; Name ; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|pll1 ;
+-------------------------------+----------------------------------------------------------------------+
; SDC pin name U_SYS_PLL|altpll_component|auto_generated|pll1 ;
; PLL mode Normal ;
; Compensate clock clock0 ;
; Compensated input/output pins -- ;
; Switchover type -- ;
; Input frequency 0 30.0 MHz ;
; Input frequency 1 -- ;
; Nominal PFD frequency 30.0 MHz ;
; Nominal VCO frequency 600.0 MHz ;
; VCO post scale K counter 2 ;
; VCO frequency control Auto ;
; VCO phase shift step 208 ps ;
; VCO multiply -- ;
; VCO divide -- ;
; Freq min lock 15.0 MHz ;
; Freq max lock 32.51 MHz ;
; M VCO Tap 0 ;
; M Initial 1 ;
; M value 20 ;
; N value 1 ;
; Charge pump current setting 1 ;
; Loop filter resistance setting 24 ;
; Loop filter capacitance setting 0 ;
; Bandwidth 450 kHz to 980 kHz ;
; Bandwidth type Medium ;
; Real time reconfigurable Off ;
; Scan chain MIF file -- ;
; Preserve PLL counter order Off ;
; PLL location PLL_1 ;
; Inclk0 signal MBT_CLK ;
; Inclk1 signal -- ;
; Inclk0 signal type Dedicated Pin ;
; Inclk1 signal type -- ;
+-------------------------------+----------------------------------------------------------------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Usage ;
+----------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+
; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ;
+----------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+
; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; clock0 ; 10 ; 3 ; 100.0 MHz ; 0 (0 ps) ; 7.50 (208 ps) ; 50/50 ; C0 ; 6 ; 3/3 Even ; -- ; 1 ; 0 ; U_SYS_PLL|altpll_component|auto_generated|pll1|clk[0] ;
+----------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+

------------------ BAD PROJECT -----------------------

+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Summary ;
+-------------------------------+----------------------------------------------------------------------+--------------------------------------------------------------------------------------+
; Name ; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|pll1 ; adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_altpll_gr22:sd1|pll7 ;
+-------------------------------+----------------------------------------------------------------------+--------------------------------------------------------------------------------------+
; SDC pin name U_SYS_PLL|altpll_component|auto_generated|pll1 U_SYS_ADC|adc1_pll|sd1|pll7 ;
; PLL mode Normal Normal ;
; Compensate clock clock0 clock0 ;
; Compensated input/output pins -- -- ;
; Switchover type -- -- ;
; Input frequency 0 30.0 MHz 10.0 MHz ;
; Input frequency 1 -- -- ;
; Nominal PFD frequency 30.0 MHz 10.0 MHz ;
; Nominal VCO frequency 600.0 MHz 400.0 MHz ;
; VCO post scale K counter 2 2 ;
; VCO frequency control Auto Auto ;
; VCO phase shift step 208 ps 312 ps ;
; VCO multiply -- -- ;
; VCO divide -- -- ;
; Freq min lock 15.0 MHz 7.5 MHz ;
; Freq max lock 32.51 MHz 16.25 MHz ;
; M VCO Tap 0 0 ;
; M Initial 1 1 ;
; M value 20 40 ;
; N value 1 1 ;
; Charge pump current ; setting 1 setting 1 ;
; Loop filter resistance ; setting 24 setting 20 ;
; Loop filter capacitance ; setting 0 setting 0 ;
; Bandwidth ; 450 kHz to 980 kHz 450 kHz to 590 kHz ;
; Bandwidth type ; Medium Medium ;
; Real time reconfigurable ; Off Off ;
; Scan chain MIF file ; -- -- ;
; Preserve PLL counter order ; Off Off ;
; PLL location ; Unassigned Unassigned ;
; Inclk0 signal OBE_CLK ; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[3] ;
; Inclk1 signal -- -- ;
; Inclk0 signal type Dedicated Pin Global Clock ;
; Inclk1 signal type -- -- ;
+-------------------------------+----------------------------------------------------------------------+--------------------------------------------------------------------------------------+

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; PLL Usage ;
+--------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+
; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ;
+--------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+
; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0] ; clock0 ; 4 ; 1 ; 120.0 MHz ; 0 (0 ps) ; 9.00 (208 ps) ; 50/50 ; C0 ; 5 ; 3/2 Odd ; -- ; 1 ; 0 ; U_SYS_PLL|altpll_component|auto_generated|pll1|clk[0] ;
; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[2] ; clock2 ; 1 ; 1 ; 30.0 MHz ; 0 (0 ps) ; 2.25 (208 ps) ; 50/50 ; C1 ; 20 ; 10/10 Even ; -- ; 1 ; 0 ; U_SYS_PLL|altpll_component|auto_generated|pll1|clk[2] ;
; pll:U_SYS_PLL|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[3] ; clock3 ; 1 ; 3 ; 10.0 MHz ; 0 (0 ps) ; 0.75 (208 ps) ; 50/50 ; C2 ; 60 ; 30/30 Even ; -- ; 1 ; 0 ; U_SYS_PLL|altpll_component|auto_generated|pll1|clk[3] ;
; adc_qsys:U_SYS_ADC|adc_qsys_ADC1_PLL:adc1_pll|adc_qsys_ADC1_PLL_altpll_gr22:sd1|wire_pll7_clk[0] ; clock0 ; 1 ; 1 ; 10.0 MHz ; 0 (0 ps) ; 1.13 (312 ps) ; 50/50 ; C0 ; 40 ; 20/20 Even ; -- ; 1 ; 0 ; U_SYS_ADC|adc1_pll|sd1|pll7|clk[0] ;
+--------------------------------------------------------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------------------------+

In the latter report Fitter detecs two PLL's.