Honored Contributor
Honored Contributorf your fifo has power of 2 as the number of entries, than it 'rdusedw' will show 0, but it will also show 'full' (or 'rdfull' in case of a dcfifo) set to 1. if you prefix the the 'rdusedw' with this 'full' flag you get the exact representation. e.g. a 'full' fifo with 128 entries has "0000000" as the 'rdused' value, if you prefix the 'full' flag you get "10000000" which represents the 128. In dcfifo you can set set the "ADD_USEDW_MSB_BIT" to "ON" to get the correct 'rdusedw' representation directly.
I advise you to read the user guides for the fifos thoroughly though, as there a few other pitfalls with latency and such, e.g. the 'full' flag may be one clock ahead of the 'rdusedw' value indicating "11111111" just before giving the correct "10000000". --- Quote Start --- Fifos may show unpredictable behaviour if you write to a full one. Best practice is to optimise the operating point near the middle. If it gets full you must have logic to return back to this optimum point. If your fifo is dc then check your reset operation. --- Quote End --- You can write safely to full fifo, if you didn't turn off the OVERFLOW_CHECKING setting (which is default set to "ON"). Optimising the operating point to the middle may waste a lot of memory, I'd rather say you optimise you system to keep fifos empty, but make them big enough to handle the bursts
