Altera_Forum
Honored Contributor
Honored ContributorA bug in qmegawiz command line?
I want to use qmegawiz command line generate a 2 ports ram with clock_a and clock_b.
"qmegawiz -silent module=altsyncram -f:ram_params.txt myram.v" the content in file ram_params.txt as follows: address_aclr_a=NONE address_aclr_b=NONE address_reg_b=CLOCK1 indata_aclr_a=NONE indata_aclr_b=NONE indata_reg_b=CLOCK1 intended_device_family=Stratix lpm_type=altsyncram numwords_a=256 numwords_b=1024 operation_mode=BIDIR_DUAL_PORT outdata_aclr_a=NONE outdata_aclr_b=NONE outdata_reg_a=UNREGISTERED outdata_reg_b=UNREGISTERED power_up_uninitialized=FALSE read_during_write_mode_mixed_ports=DONT_CARE widthad_a=8 widthad_b=10 width_a=4 width_b=1 width_byteena_a=1 width_byteena_b=1 wrcontrol_aclr_a=NONE wrcontrol_aclr_b=NONE wrcontrol_wraddress_reg_b=CLOCK1 but the result file myram.v is only one clock! as follows; altsyncram_component.address_aclr_a = "NONE", altsyncram_component.address_aclr_b = "NONE", altsyncram_component.address_reg_b = "CLOCK0", altsyncram_component.indata_aclr_a = "NONE", altsyncram_component.indata_aclr_b = "NONE", altsyncram_component.indata_reg_b = "CLOCK0", altsyncram_component.intended_device_family = "Stratix", altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 256, altsyncram_component.numwords_b = 1024, altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_aclr_b = "NONE", altsyncram_component.outdata_reg_a = "UNREGISTERED", altsyncram_component.outdata_reg_b = "UNREGISTERED", altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", altsyncram_component.widthad_a = 8, altsyncram_component.widthad_b = 10, altsyncram_component.width_a = 4, altsyncram_component.width_b = 1, altsyncram_component.width_byteena_a = 1, altsyncram_component.width_byteena_b = 1, altsyncram_component.wrcontrol_aclr_a = "NONE", altsyncram_component.wrcontrol_aclr_b = "NONE", altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; when i use gui to genrate 2 pots ram with clock_a and clock_b the parameter is just as follows: only CLOCK1 altsyncram_component.address_aclr_a = "NONE", altsyncram_component.address_aclr_b = "NONE", altsyncram_component.address_reg_b = "CLOCK1", altsyncram_component.indata_aclr_a = "NONE", altsyncram_component.indata_aclr_b = "NONE", altsyncram_component.indata_reg_b = "CLOCK1", altsyncram_component.intended_device_family = "Stratix", altsyncram_component.lpm_type = "altsyncram", altsyncram_component.numwords_a = 32, altsyncram_component.numwords_b = 64, altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_aclr_b = "NONE", altsyncram_component.outdata_reg_a = "UNREGISTERED", altsyncram_component.outdata_reg_b = "UNREGISTERED", altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.widthad_a = 5, altsyncram_component.widthad_b = 6, altsyncram_component.width_a = 8, altsyncram_component.width_b = 4, altsyncram_component.width_byteena_a = 1, altsyncram_component.width_byteena_b = 1, altsyncram_component.wrcontrol_aclr_a = "NONE", altsyncram_component.wrcontrol_aclr_b = "NONE", altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
