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Honored Contributor
Honored Contributor8b10b clock recovery?
Would it be possible to use an Altera FPGA (Arria II GX or Cyclone IV GX) to snoop on a 2.5 Gbps PCI Express link (via the PIPE interface), recover the clock and send out the recovered clock to one o...
Altera_ForumHonored Contributor
Honored ContributorI saw a block diagram of a Mindspeed 4 channel CDR, that has Data inputs and Clock + Data outputs. Clock means recovered clock in my understanding.
As I previously mentioned, the PCIe Refclk can be used as a trigger for jitter measurements, because all Tx signals are phase locked to it. See also PCie 2.0 Base Spec chapter 4.3.2. jitter budgeting and measurement for a discussion of the PCIe jitter model. If you use REFCLK as a trigger, you see the transmitter fully contributing to measured jitter. But I don't think that this is a problem in comparative measurements.
