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Altera_Forum
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16 years ago

8b10b clock recovery?

Would it be possible to use an Altera FPGA (Arria II GX or Cyclone IV GX) to snoop on a 2.5 Gbps PCI Express link (via the PIPE interface), recover the clock and send out the recovered clock to one o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I could not see any recovered clock being output from the mindspeed devices. I however did not see any datasheet but rather block diagrams.

If i'm not mistaken there is a 100 MHz reference clock that must be sent along with the differential signals. Since this should be phase aligned with the diff signals, or at the very least have low jitter in relation to the data, would it be possible to use the reference clock to trigger the scope?

Also, must i feed the differential reference clock into the Cyclone IV for it to be able to consume the differential high-speed PCI express data? I searched the Cyclone IV handbook but could not find must information (it is late, though so i might have missed it).

Thanks.