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Altera_Forum
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16 years ago

8b10b clock recovery?

Would it be possible to use an Altera FPGA (Arria II GX or Cyclone IV GX) to snoop on a 2.5 Gbps PCI Express link (via the PIPE interface), recover the clock and send out the recovered clock to one o...
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Altera_Forum
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16 years ago

Well now I understand a bit more. So you don't really need to "tap" the signal at all. The scope is your endpoint. There is no reason why you can't just use the data signal as your scope trigger. So you can go ahead and use the negated side of the pair as a trigger.

I did a fairly extensive investigation on scope triggering methods for FPGA transceiver outputs. Basically your best case jitter is if you reclock the data and use the recovered clock to trigger the scope viewing the reclocked data. Second best case jitter is to recover the clock and use it to trigger the scope viewing non-reclocked data. I tested about 8 different methods. Using the complementary data signal to trigger the scope came in 6th.

However, the test case was for pathological SDI data and your 8b/10b will perform better. Also, all you care about is rise/fall times and amplitude. You'll be fine.

Jake