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Altera_Forum
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16 years ago

8b10b clock recovery?

Would it be possible to use an Altera FPGA (Arria II GX or Cyclone IV GX) to snoop on a 2.5 Gbps PCI Express link (via the PIPE interface), recover the clock and send out the recovered clock to one o...
Altera_Forum's avatar
Altera_Forum
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16 years ago

It's not obvious to me, that a recovered CDR clock brings an advantage for your measurements. But may be I didn't understand the intention exactly. The practical problems of tapping a PCIe link without disturbing it should be well considered. A differential active probe would be the best solution. A matched resistive "power divider" involves a 6 dB attenuation.

Most PCIe system are using a spread spectrum reference clock, which adds additional jitter to any PLL or recovery circuit, that locks to the clock. All PCIe Tx signals are however locked to the 125 MHz reference clock, so you may want to try, if this clock isn't suitable for triggering the measurements. It's jitter should be "two PLL steps" lower than your intended CDR circuit.