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Honored Contributor
Honored Contributor8b10b clock recovery?
Would it be possible to use an Altera FPGA (Arria II GX or Cyclone IV GX) to snoop on a 2.5 Gbps PCI Express link (via the PIPE interface), recover the clock and send out the recovered clock to one o...
Altera_ForumHonored Contributor
Honored ContributorThanks for the Mindspeed link. It looks like none of their circuits actually output a clock but are used for re-sending high-speed serial data.
When thinking a bit more about the problem; is it even neccesary to recover the clock? I am only interested in the behavior of the rising and falling edges as well as the corresponding ampliture. Doesn't this mean that i can trigger on any rising/falling edges and that the underlying clock therefore is irrelevant? The end destination of the PCI Express link is the oscilloscope itself. The differential signal pair will go from the motherboard, through the extender board, through the load board (that has the SMA connectors) and into the oscilloscope where the signals are terminated in 50 ohm. In other words, the 'load board' is really just a PCIe board that connects all downstream differential signals to SMA connectors. Thanks.
