Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributor8 MHz clock from 100 MHz
I am generating 8 MHz clock by scaling down the 100 MHz clock. The design I have implemented simulates well but when loaded on MAX-10 and observed using Signal Tap II logic analyzer the clock signal ...
Altera_ForumHonored Contributor
Honored ContributorPLLs do not require additional licensing.
Where is the 50 MHz clock you are using for sampling coming from?
