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Altera_Forum
Honored Contributor
Honored Contributor8 MHz clock from 100 MHz
I am generating 8 MHz clock by scaling down the 100 MHz clock. The design I have implemented simulates well but when loaded on MAX-10 and observed using Signal Tap II logic analyzer the clock signal ...
Altera_ForumHonored Contributor
Honored ContributorYou may be undersampling in Signal Tap depending on what you are using as the sampling clock in the tool. Why don't you just use a PLL?
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/ug_m10_clkpll.pdf
