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Thanks! That is what I really need.
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Keep in mind that if you are driving the inputs of the FPGAs with a buffer, that the FPGA pull-ups are no longer any use. It will be the input to the external buffer that determines what logic level is on the FPGA inputs.
So, if your buffer is going to be driven by signals that can be removed, eg., are going to a connector, then you need to put pull-ups or downs on the signals
at the input to the buffer so that they do not float when the connector is removed, assuming the FPGA is still powered in that situation. You can save yourself some pull-ups by using a buffer with bus-hold, however, if you want a specific logic level, then using pull-ups and downs allows you to do that.
Be careful with the pull-ups, you do not want to tie them to the 3.3V rail of the buffer, since you will be driving them with 5V and then your I/O pin might try to power your FPGA board if you power it down while the 5V I/O is high. Ideally you should use pull-downs on the buffer inputs.
Cheers,
Dave
Honored Contributor
