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ShivaKi's avatar
ShivaKi
Icon for New Contributor rankNew Contributor
1 year ago

5CEBA7F27C8N FPGA IO Pin Status After Power ON Reset

Hello, For FPGA 5CEBA7F27C8N, 1. What will be the status of IO Pins after Power ON Reset, when IO pins are configured as a. Input b.Output c. Input/Output 2. What will be the stat...
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AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

Hello,


  1. After Power On Reset (POR), all the I/Os pins are tied to an internal weak pull-up before entering the user mode.
  2. After functional reset, the I/O pins will behave following the logic you assigned in your code. It is dependent on the design itself.


Regards,

Aqid