Forum Discussion
ShivaKi
New Contributor
New Contributor5CEBA7F27C8N FPGA GPIO Pins Setup and Hold time
Hello, For FPGA 5CEBA7F27C8N, a parallel interface to be implemented using GPIO pins. While performing write operation into FPGA from external processor, 1. what will be the setup and holdtime of...
AqidAyman_Altera
Regular Contributor
Regular ContributorHi,
I am not an expert in the timing area, but I know that you can use a logic setting inside Quartus to see if the setup and hold time was violated. Refer to link below:
