Forum Discussion

SGADKSRI's avatar
SGADKSRI
Icon for New Contributor rankNew Contributor
1 year ago

5CEBA7F27C8N FPGA Flipflop(FF) placement setting

Hi Teams, For 5CEBA7F27C8N FPGA, please find below queries needed clarification. 1. What is meant by "IO Flipflop Configuration Settings" in FPGA design? 2. For what kind of signals, this Flipflo...
Configuration
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi Sanju,


These links can help you:

https://www.intel.com/content/www/us/en/docs/programmable/683283/18-1/use-i-o-flipflops.html

https://www.intel.com/content/www/us/en/docs/programmable/683641/21-3/fast-input-output-and-output-enable.html


enable flipflops (or registers) in I/O cells that have fast, direct connections to an I/O pin, when possible. To improve I/O performance by minimizing setup, clock-to-output, and clock-to-output enable times


Usually use for input/output signals.