40 Gbps QSFP arria 10 analog parameters

Hi,

Transceiver PMA analog parameter link tuning process is very dependent on the board design.

• Different board may required to use different PMA setting

For Intel FPGA side, our Arria 10 "low latency 40G Ethernet IP" example design is verified using "Arria 10 GX Transceiver Signal Integrity Development Kit"

• You can find out more about the example design in below link but as I said the PMA setting may not be suitable to you since you are using different board
• https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/deug_ll_40ge.pdf

I can see that you are using Terasic TR10a-LP dev kit board, then my suggestion is why not you consult Terasic directly.

• Ask them how they validate 40G Eth transaction on their board ?
• Is there any 40G Eth reference design that can share with you ?
• You can try reach out to Terasic via [email protected]

Thanks.

Regards,

dlim