32-bit SSRAM must have byteenable for Nios II?

Jake -

Thanks a lot. Yes, you are absolutely right, the goal is to save a few IO pins. Unfortunately, I plan to use external SRAM for instructions and data.

To be byte addressable, given the constraint of IO pins, it seems that now I have to reduce data bus width from 32-bit to 16-bit (by using 16-bit SRAM). If I do that, I assume my system performance will be reduced by half (rougly) -- due to the reason that for each 32-bit instruction, CPU has to fetch twice instead of once. Is that right?

Thanks again for your help!!

FZ

If you plan to write less than a full word (32 bits) at a time then you must have the byte enables. The NIOS expects it's instruction and data memories to be byte addressable. If you are going to use the SRAM as instruction or data memory for the NIOS then you must connect the byte enables. This is the only mechanism available to the processor for performing byte-addressed writes to an interface that is greater than 8-bits wide.

The only way you could get around it would be to do a read-modify-write every time you wanted to write less than 32-bits. Read the data from the SRAM, modify the byte(s) that are being written to and write the data back out. This is a huge inefficiency (defeats the purpose of using SRAM in the first place) and you would have to write your own controller to do this as it would have to be transparent to the processor.

If you are not going to use the SRAM for NIOS instruction or data memory; that is if you are going to use it for your own purposes and you will control the writing of data to the memory, then you could certainly only do 32-bit writes if it fits your design needs. I assume your motivation is to save pins.

Jake