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Altera_Forum's avatar
Altera_Forum
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11 years ago

27 MHz from 50 or 125 MHz?

Hello all,

I am working on a project in which I need a 27MHz clock for the VGA interface.

I am using Cyclone III 3c120 FPGA and it has only 50MHz and 125MHz oscillators.

Can I get 27MHz clock using any of these oscillator inputs?

Thanks,

Suresh

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Use an ALTPLL mega-function with an input clock of 50MHz and an output clock of 27MHz, it wouldn't of thought it would have a problem achieving that.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Use an ALTPLL mega-function with an input clock of 50MHz and an output clock of 27MHz, it wouldn't of thought it would have a problem achieving that.

    --- Quote End ---

    Thanks. I tried that already before posting my question. I got the error message "Cannot implement the requested PLL. Cause: Requested mult/div factors not achievable."

    Instead it generated 27.083333 MHz clock. I wanted to know if I can generate exact 27MHz clock.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Instead it generated 27.083333 MHz clock. I wanted to know if I can generate exact 27MHz clock.

    --- Quote End ---

    Weird, when I tried it, it generated fine - said it could do the exact frequency. I've attached the core it generated (from Quartus 13, web edition).
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Thank you TCWORLD. I am using Quartus II - 13.0.1 version. I got the error when I tried to do the same as what you have done. But I don't see any error with your core. Strange, but I will try to see why there is an error in my case.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    You can easily calculate that 27 MHz can be achieved with small integer ratios. The problem may be that you are trying to generate another frequency with the same PLL which doesn't fit the divider parameters. In this case use two PLLs.