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Altera_Forum
Honored Contributor
Honored Contributor125 MHz clock+data output
I have a design with a CycloneIV that needs to talk to a GMII PHY, which expects data bytes on 8 parallel lines along with a clock signal. I use a PLL to generate a 125 MHz clock, and would now...
Altera_ForumHonored Contributor
Honored ContributorExcellent, this is pretty much what I need (except now I get to hunt segmentation faults in MegaWizard).
Thanks!
