XQSHEN
Occasional Contributor
Occasional Contributor10M16DCU324 external clock input voltage level
hello,
The external clock was connected at FPGA bank2 clock input pin.
It will be used as PLL input, and then distribute clock to all FPGA banks.
1) clock input voltage is 1.8V at bank 2.
2) the voltage level of IO at bank4 is 3.3V.
The clock was routed from PLL will be used for bank4.
Is there any problem ?
Hi,
Clock generated by an internal PLL can be routed to entire FPGA using global clock buffers. No bank voltage dependency.
Regards
