10M08DAF256 - LVDS rx-only, can IO bank be at 3.3V?

Thank you again for your response.

I understand it is not recommended and that performance is not guaranteed; the datasheet makes clear that the proper voltage for banks with LVDS is 2.5V. My question is whether the LVDS receivers will work (perhaps with degraded performance) with VCCIO at 3.3V. If the LVDS receivers will work with an out-of-spec VCCIO, what can I expect in terms of performance degradation (change of switching threshold or margin, reduced max speed, etc.) on the LVDS inputs? Surely Intel has some data on this kind of application and can give me an idea of what I might expect.

I'm trying to see whether I scrap these boards and order new ones or if I can work with the reduced performance for these prototypes, and only make the corrections on the new boards.

These are answers I cannot obtain without Intel's help.