10M08DAF256 - LVDS rx-only, can IO bank be at 3.3V?

Hello, thank you for your assistance.

This is is a prototype design which has already been laid out. The final design will of course have the correct IO voltage.

I have a number of LVDS inputs on bank 5 and 6. They are externally terminated with 100 ohm resistors. The FPGA is not transmitting any LVDS, only receiving. I have mistakenly connected bank 5 and 6 VCCIO to 3.3V instead of 2.5V as specified in the data sheet. You are correct that VREFB is not used as reference; those pins are used as regular, low speed single ended I/O.

Yes, VCCA is connected to 2.5V. VCCA_ADC and ADC_VREF are also connected to 2.5V. VCCD_PLL1/2, VCC_INT and VCC are all connected to 1.2V with filters as specified in the pin connection guidelines on page 26.

My question is if the 10M08D will be able to correctly receive 125MHz LVDS (250Mbps) on bank 5 and 6 with VCCIO at 3.3V instead of 2.5V. I am not transmitting, only receiving. I want to know if I can use these boards or if I must scrap them and re-spin the prototypes due to this mistake.

Thank you,

-A.