10M08DAF256 - LVDS rx-only, can IO bank be at 3.3V?

Thank you giving opportunity to look at issue, Can I assume few things from your input , i) You are not plan to use LVDS in the board using FPGA. Correct ? ii) The VCCIO of bank 5 and 6 connected to the 3.3V. Also Can I assume VREFBx pin is not used for reference voltage ? Correct If my above assumption yes , I don’t think so there is issue to connect the 3.3V bank 5 and bank 6 . In the datasheet can you refer page 7 for the max apply VCCIO ? Note : VCCA must connected to the 2.5V. May I know why you think bank 5 and 6 need to use only for LVDS ? Thank you, Regards, Sree