Forum Discussion
Occasional Contributor10M02SCM153C8G POWER USE
Hi,
Recommend you to follow the guidelines provided for the device on following page:
Notes to the Intel® MAX® 10 FPGA Pin Connection Guidelines
The above link mainly recommends placement of the capacitors, but eventually user should be doing the board level simulations to check signal integrity of the board.
As you rightly said, the power consumption depends a lot on the design. For the power consumption estimation use the Early Power Estimator tool:
MAX 10 PowerPlay Early Power Estimator (EPE) | Intel
Regards
Regular ContributorHi,
It is recommended that you keep the 0.1uF caps near to the power pins to supply optimal current as required during operation. Hence, suggest you to please follow the Power Distribution Tool recommendation.
Power Distribution Network (PDN) | Intel
Regards
- FvM
Super Contributor
Hi,
our standard solution is having bypass capacitors at every supply pin at bottom side, preferably connected by VIPPO pins. But actual minimal bypass requirement depends a lot on switching activity and load impedance. We also made single side populated boards with bypass capacitors beside the FPGA package and also functional designs with PQFP packages in the past.
