Forum Discussion

Honored Contributor

9 years ago

10M02DCV36I7G - cheap, reliable clocking

I am new to MAX10s and pretty new to FPGAs in general, and will be using 10M02DCV36I7G as a peak detector. The inputs come from two single-ended comparator outputs. I plan to use a number of ph...

Altera_Forum

Honored Contributor

9 years ago

Interesting.

Do you think in such a comparator setup, that I could use the LVDS/LVPECL input as a clock input, with FFs clocking off both the rising and falling edges?

That would allow me to capture the comparator events with practically no delay.

https://s4.postimg.org/hhc5yudzh/fpga_clock_input.png (https://postimg.org/image/40f7fz3nt/)free upload (https://postimage.org/)

Forum Discussion

10M02DCV36I7G - cheap, reliable clocking

Recent Discussions

Cyclone 5 SoC FPGA Bank Supply Prerequisite

AGILEX 5 Migration issue

To INTEL - Request for Compliance Data from Analog Devices, Inc

Arria 10 GX RX max intra-differential pair skew

MAX10 Bitstreams Authentication