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Honored Contributor
Honored Contributor10M02DCV36I7G - cheap, reliable clocking
I am new to MAX10s and pretty new to FPGAs in general, and will be using 10M02DCV36I7G as a peak detector. The inputs come from two single-ended comparator outputs. I plan to use a number of ph...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Are there considerably power savings to having a low scaling factor between oscillator input and PLL output? Or other advantages? --- Quote End --- Dynamic power dissipation in CMOS is directly related to switching frequency, so slowing the clocks down will definitely reduce power. But that would be more in the clock trees and logic fabric. The power savings in the PLL itself would probably not be significant.
