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The point is to do peak detection, so there is not a lot involved at the high frequency. I could run a lower main frequency, and synchronize the peak detectors to that. Four phases of 400 MHz is not a hard requirement, but I am looking to minimize the timing uncertainty when detecting the peaks, and trying to uncover the pros and cons of various solutions.
Thanks for pointing out the HW limitations and jitter concerns, which are of course important. The Si5338 is waaaay too expensive unfortunately. I have to keep this dirt cheap.
Given the high jitter and other concerns, it might make sense to run four phases of 200 MHz.
Are there considerably power savings to having a low scaling factor between oscillator input and PLL output? Or other advantages?
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I'm a bit unclear on the peak detection process, could you elaborate? I don't think there are significant power savings with PLL scaling factors but others may have more knowledge here.
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