10G Ethernet and 10G Base-R PHY Hardware Demonstration Design

Dear Dave,

With my purpose of having a board-to-board 10GbE design, I have focused more in hardware test of the functionality of MAC or/and PHY layer. So, I have spent days to study this design (10G Ethernet and 10G Base-R PHY) and similar Altera reference designs such as:

10-Gbps Ethernet Reference:

http://www.altera.com/literature/ug/10g_ethernet_user_guide.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=10-gbps%20ethernet%20reference%20design%20user%20guide

10-Gbps Ethernet MAC and XAUI PHY Interoperability Hardware Demonstration:

http://www.altera.com/literature/an/an638.pdf?gsa_pos=6&wt.oss_r=1&wt.oss=10-gbps%20ethernet%20reference%20design%20user%20guide

Triple Speed Ethernet Data Path Reference Design:

http://www.altera.com/literature/an/an483.pdf

Stratix II GX 10GbE Loopback Reference Design

http://www.altera.com/literature/an/an561.pdf

And I found out that all the reference/example designs provided by Altera only support several loopback tests, either internal or local (external) loopback. While board-to-board testing is also necessary and more difficult (my personal thinking), Altera do not provide any demo tests. And so far, I even could not find related tutorials anywhere. How should we understand this situation? If you can share your opinion or suggest me a way to go on with my target design.

Thank you very much.