10G Ethernet and 10G Base-R PHY Hardware Demonstration Design

Dear Dave,

I could make the board-to-board test run at receiver side without the "master_write_32" error.

The monitor logic has a base address and several offsets for statistics:

set MON_BASE_ADDR 0x01040000

set MON_RXPKTCNT_EXPT 0x00000000

set MON_RXPKTCNT_GOOD 0x00000004

set MON_RXPKTCNT_BAD 0x00000008

set MON_RXBYTECNT_LO32 0x0000000C

set MON_RXBYTECNT_HI32 0x00000010

set MON_RXCYCLCNT_LO32 0x00000014

set MON_RXCYCLCNT_HI32 0x00000018

set MON_RXCTRL_STATUS 0x0000001C

set GEN_MON_LPBK 0x00000028

I started generating and monitoring at both sides manually and almost at the same time. At RX side, the system console log shows that the monitor is unable to receive any packet. That means the above memory locations are not touched during the transmission. How can I explain and fix this? If you have any suggestion for debugging?

Here is how the traffic controller works. The traffic generator at transmitter generates packets of different types, with random length(<=1518) and random payload then sends them in burst to receiver. The monitor at receiver just checks number of received packets, how many with errors, how many of each types,... In case I have a board-to-board test, my next step is to check the transmission, namely to compare the difference of data sent at TX and data received at RX. But, I still don't know whether packet contents are temporary stored somewhere at both sides or not. How do you think about this plan?

Again, I need to understand the memory map. I could not find how the addresses are mapped and allocated in the design. I think this is a critical point for me now. Please help to give me a clue if possible.

Thanks.