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Altera_Forum
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14 years ago

10G Ethernet and 10G Base-R PHY Hardware Demonstration Design

Hi all, I am trying to test board-to-board communication using a complete 10G Ethernet design that includes an Altera 10 GbE MAC + an Altera 10GBASE-R IP cores. My devices are Stratix IV GT and...
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Altera_Forum
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14 years ago

You can check the Qsys system in the attachment. They use a Merlin Master Translator and there is only one Master-Slave connection here is between Merlin Master Translater->Eth_10g mm_pipeline_bridge (slave). I don't know why they do not use the Jtag to Avalon as a Master? What is the role of the Merlin Master Translator? is it used here like a Jtag to Avalon Master?