10G Ethernet and 10G Base-R PHY Hardware Demonstration Design

From your code:

ETH10G_TOP  ETH10G_TOP (
    .mm_clk_clk                            (clk_50),
    .mm_reset_reset_n                    (RESET_N),
                                        
    .mm_pipeline_bridge_address            (slave_if_address),
    .mm_pipeline_bridge_waitrequest        (slave_if_waitrequest),
    .mm_pipeline_bridge_read            (slave_if_read),
    .mm_pipeline_bridge_readdata        (slave_if_readdata),
    .mm_pipeline_bridge_write            (slave_if_write),
    .mm_pipeline_bridge_writedata        (slave_if_writedata),
    
    .xgmii_rx_clk_clk                    (rx_phy_clk),
    .link_fault_status_xgmii_rx_data    (link_fault_status),
    
    .tx_serial_data_export                (TXP_10G_BASE_R),
    .rx_serial_data_export                (RXP_10G_BASE_R),
    
    .ref_clk_clk                        (REFCLK),
    .ref_reset_reset_n                    (RESET_N),
    
    .avalon_st_rxstatus_valid            (rx_status_valid),
    .avalon_st_rxstatus_data            (rx_status_data),
    .avalon_st_rxstatus_error            (rx_status_error),
    .avalon_st_txstatus_valid            (),
    .avalon_st_txstatus_data            (),
    .avalon_st_txstatus_error            (),
    
    .tx_ready_export                    (tx_pma_ready),
    .rx_ready_export                    (rx_pma_ready),
    
    .rx_sc_fifo_out_data                (avalon_st_rx_data),
    .rx_sc_fifo_out_valid                (avalon_st_rx_valid),
    .rx_sc_fifo_out_ready                (avalon_st_rx_ready),
    .rx_sc_fifo_out_startofpacket        (avalon_st_rx_sop),
    .rx_sc_fifo_out_endofpacket            (avalon_st_rx_eop),
    .rx_sc_fifo_out_empty                (avalon_st_rx_empty),
    .rx_sc_fifo_out_error                (avalon_st_rx_error),
    
    .tx_sc_fifo_in_data                    (avalon_st_tx_data),
    .tx_sc_fifo_in_valid                (avalon_st_tx_valid),
    .tx_sc_fifo_in_ready                (avalon_st_tx_ready),
    .tx_sc_fifo_in_startofpacket        (avalon_st_tx_sop),
    .tx_sc_fifo_in_endofpacket            (avalon_st_tx_eop),
    .tx_sc_fifo_in_empty                (avalon_st_tx_empty),
    .tx_sc_fifo_in_error                (avalon_st_tx_error),
    
    .mdio_mdc                           (mdc_from_the_mdio),
    .mdio_mdio_in                        (mdio_in_to_the_mdio),
    .mdio_mdio_out                        (mdio_out_from_the_mdio),
    .mdio_mdio_oen                       (mdio_oen_from_the_mdio),    
    
    .tx_clk_clk                            (rx_phy_clk),
    .tx_reset_reset_n                    (RESET_N) 
); 

There is both an MDIO interface and an Avalon slave interface. The slave should show up in your address map, and there should be registers for an MDIO controller (I assume this is an I2C controller that never actually exits the FPGA).

Cheers,

Dave