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suvarna's avatar
suvarna
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10 days ago

10CL040YF484 Programming fails

1st Vendor Batch (Date Code: 2525):           - First Test (3 FPGAs):           - Card 1: ISP and JTAG programming successful; functioning correctly.           - Card 2: Programmed in ISP mode, ...
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FvM's avatar
FvM
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8 days ago

Hi Survarna,
reviewing your schematic, I notice that it fails to set AS configuration mode due to floating MSEL1. For apparently intended mode 0010, MSEL1 has to be connected to 3.3V. FPGA actually reads mode 0000 (PS) and won't load AS flash. Volatile JTAG configuration should nevertheless work.

Regarding JTAG failure (programmer doesn't detect connected FPGA), you can focus on JTAG connection and FPGA power supply. All POR monitored voltages must be present and in range.

Isolation of GNDA pins through ferrite bead isn't complying with Altera pin connection guidelines but probably does no harm. I would also prefer a LDO for 2.5V PLL supply.

I believe that I last implemented separate AS programming ("ISP") connector 15 or 20 years ago. Since then we used JIC programming through JTAG connector.

I understand that failing and (at least partly) working boards share the same hardware design.

Regards
Frank

  • suvarna's avatar
    suvarna
    Icon for New Contributor rankNew Contributor
    8 days ago

    Dear Sir,

    MSEL1 pin i gave resistor option for 3.3v or 2.5v  at present in cards i connected msel1 to 2.5v side resistor. all cards are belonging to same pcb same hardware design we assemble the pcbs in 3 batches. 

    is TPS563209  not suitable for PLL 2.5V supply ? we used 3 seperate regulators for 3.3V,1.2V,2.5V.