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Jq6313's avatar
Jq6313
Icon for New Contributor rankNew Contributor
2 years ago

10CL016YF484C8G Power On Sequence

Does anyone know if there is a supply rail power on sequence for this FPGA? As in does the supply rails have to be powered in a certain order?
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,
the information is a bit hidden in device handbook paragraph 9.4 Power-on reset circuitry:


The POR circuit of the Intel Cyclone 10 LP device monitors the VCCINT, VCCA, and VCCIO (of banks 1, 5, 6, and that contain configuration pins during power-on. You can power up or power down the VCCINT, VCCA, and VCCIO pins in any sequence. The VCCINT, VCCA, and VCCIO must have a monotonic rise to their steady state levels. All VCCA pins must be powered to 2.5V (even when phase-locked loops [PLLs] are not used), and must be powered up and powered down at the same time.