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Altera_Forum
Honored Contributor
8 years ago10779 VHDL ERROR : expression is not constant
Hello guys, I am writing VHDL code in Quartus Prime 15.1 Lite Edition. I have problem when I was doing Analysis and Synthesis. The error is expression is not constant. I can use that data(a d...
Altera_Forum
Honored Contributor
8 years agoI added my code file, When u are going to look my code, I express the error command near to my code.
I hope u will find solution . Thank u ...