Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

10779 VHDL ERROR : expression is not constant

Hello guys, I am writing VHDL code in Quartus Prime 15.1 Lite Edition. I have problem when I was doing Analysis and Synthesis. The error is expression is not constant. I can use that data(a d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

But it could be that this is still a problem, and you'll have to work around it. Usually you can do this with a case statement instead of a slice