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Honored Contributor10779 VHDL ERROR : expression is not constant
Hello guys, I am writing VHDL code in Quartus Prime 15.1 Lite Edition. I have problem when I was doing Analysis and Synthesis. The error is expression is not constant. I can use that data(a d...
Altera_ForumHonored Contributor
Honored ContributorBut it could be that this is still a problem, and you'll have to work around it. Usually you can do this with a case statement instead of a slice
