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Altera_Forum
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7 years ago

10779 VHDL ERROR : expression is not constant

Hello guys, I am writing VHDL code in Quartus Prime 15.1 Lite Edition. I have problem when I was doing Analysis and Synthesis. The error is expression is not constant. I can use that data(a d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

you didnt attach the code, just a tiny snippet. Please post the whole code so we can see whats going on. Not just the line with the issue.